Switched mode power supplies are well known in the art. For example, FIG. 1 shows an example of a DC-DC boost converter. Specifically, the converter comprises two input terminals 102a and 102b for receiving a DC input voltage VIN, wherein the negative input terminal 102b represents a ground GND. The converter comprises also two output terminals 104a and 104b for providing a regulated DC output voltage VOUT. Specifically, in case of a conventional boost converter, the output voltage VOUT is (equal to or) greater than the input voltage VIN.
For example, the input voltage VIN may be provided by any DC power source, such as a battery or a rectified AC voltage, and the output voltage VOUT may be used to power a load. Accordingly, in operation, the output terminals 104a and 104b will provide a current IOUT to a load connected between the terminals 104a and 104b. 
A boost converter typically comprises an inductive energy storage element L, e.g. an inductor, and a diode D, which are connected (e.g. directly) in series between the positive input terminal 102a and the positive output terminal 104a. Specifically, a first terminal of the inductor L is connected (e.g. directly) to the terminal 102a and a second terminal of the inductor L, identified in the following as node Lx, is connected (e.g. directly) to the anode of the diode D and the cathode of the diode D is connected (e.g. directly) to the positive output terminal 104a. Accordingly the diode D is configured to conduct current only in the direction of the load. Usually, the (negative) output terminal 104b is connected (e.g. directly) to ground GND. A boost converter often comprises also an output capacitor COUT connected (e.g. directly) between the output terminals 104a and 104b for stabilizing the output voltage VOUT.
In the example considered, the boost converter comprises moreover an electronic switch Q1, usually a transistor, such as field-effect transistor FET, such as a metal-oxide-semiconductor field-effect transistor (MOSFET). Due to the connection to ground GND, usually a n-channel FET (e.g. a NMOS) is used for the transistor Q1. Specifically, this transistor Q1 is configured to selectively connect the node Lx (i.e. the intermediate point between the inductive element L and the diode D) to ground GND as a function of a drive signal DRV1, i.e. the transistor Q1 is connected (e.g. directly) between the node Lx and ground GND. For example, when considering a n-channel FET, the source terminal of the transistor Q1 may be connected to ground GND/terminal 102b and the drain terminal of the transistor Q1 may be connected to the node Lx.
As shown in FIG. 2, when the transistor Q1 is closed during a switch on interval TON1 (see FIG. 2a) a current IIN flows from the positive input terminal 102a and through the inductor L to ground GND, and the inductor L stores energy by generating a magnetic field (see FIG. 2b). Conversely, when the transistor Q1 is opened during a switch on interval TOFF1, the current IIN will be reduced as the voltage VOUT is higher than the voltage VIN and the previously created magnetic field will generate a current flow through the diode D and towards the positive output terminal 104a, i.e. the capacitor COUT and the load.
Accordingly, as shown in FIG. 2a, the drive signal DRV1 corresponds to a pulsed signal, which is periodically set to a first logic level, e.g. high, thereby closing the transistor Q1 for duration TON1; and to a second logic level, e.g. low, thereby opening the transistor Q1 for duration TOFF1.
In the example considered, the converter comprises thus a control circuit 20 configured to control the operation of the boost converter, in particular the generation of the drive signal DRV1. For example, often this control circuit 20 performs a closed loop control operation in order to control the switching of the transistor Q1 as a function of a feedback signal FB indicative of the output voltage VOUT and/or the output current IOUT, in order to regulate the output voltage VOUT and/or the output current IOUT to a desired value.
For example, the circuit may comprise a voltage divider comprising at least two resistors R1 and R2, which are connected in series between the output terminals 104a and 104b, i.e. in parallel with the output capacitor COUT. Accordingly, based on the well-known operation of a voltage divider, the intermediate point between the resistors R1 and R2 provides a (voltage) signal FB indicative of (i.e. proportional to) the output voltage VOUT.
Additionally or alternatively, a current sensor may be used to generate a feedback signal FB indicative of the current IOUT, such as a shunt resistor connected in series with the terminals 104a and 104b. 
In the example considered, the feedback signal FB is provided to the control unit 20, which controls the switching operation of the transistor Q1 as a function of the feedback signal FB. Different control schemes may be implemented within the control unit 20 for controlling the transistor Q1 as a function of the feedback signal(s) FB, which are well known to those skilled in the art.
For example, usually the control circuit 20 comprise a driver circuit 22 and a regulator circuit 24.
In a first type of control scheme, the drive signal DRV1 corresponds to a pulse-width-modulation (PWM) signal, i.e. the driver circuit 22 is a PWM driver circuit. In this case, the signal DRV1 is set for the duration TON1 to the first logic level and for the duration TOFF1 to the second logic level, wherein the duration TSW1=TON1+TOF1F of a switching cycles is constant (see also FIG. 2a). For example, in this case, the regulator circuit 24 may be an error amplifier 24, such as a PI (Proportional-Integral) or PID (Proportional-Integral-Derivative) regulator, which is configured to regulate the duty-cycle DC1=TON1/TSW1 of the drive signal DRV1 as a function of the feedback signal FB until the feedback signal FB corresponds to a reference signal REF, e.g.: increase the duty-cycle DC1 when the feedback signal FB is smaller than a reference signal REF; and decrease the duty-cycle DC1 when the feedback signal FB is greater than a reference signal REF.
In a second control scheme, instead of using a PWM signal, the error amplifier 24 could also vary only one of the durations TON1 and TOFF1 (i.e. the other of the durations TON1 and TOFF1 may be constant), e.g.: increase the duration TON1 or decrease the duration TOFF1 when the feedback signal FB is smaller than a reference signal REF; and decrease the duration TON1 or increase the duration TOFF1 when the feedback signal FB is greater than a reference signal REF
In a third control scheme, the regulator circuit 24 may also comprise only a simple comparator, which compares the feedback signal FB with the reference signal REF. In this case, the regulator circuit 24 may drive the driver circuit 22 in order to generate a plurality of (short) pulses with fixed/predetermined durations TON1 and TOFF1 until the feedback signal FB is greater than the reference signal REF. Accordingly, once the feedback signal FB is greater the reference signal REF, no pulses are generated, i.e. TON1=0. Conversely, when the feedback signal FB is again smaller than the reference signal REF, the regulator circuit 24 may again drive the driver circuit 22 in order to generate one or more further pulses with fixed/predetermined durations TON1 and TOFF1. In this case, instead of using a single reference signal REF, also an upper threshold may be used to stop the pulse generation and a lower threshold may be used to start again the pulse generation. Usually, this type of driving is called burst-mode.
Generally, the above schemes may also be combined, e.g. the burst-mode may be used for small output loads and the PWM mode may be used for greater output loads, thereby avoiding that the boost converter is operated with small duty cycles resulting in a Discontinuous Conduction Mode (DCM) operation, in which the losses typically increase. For example, FIG. 2c shows the operation in the DCM mode, wherein the current reaches zero before a new cycle is started.
Thus, generally, the regulator circuit 24 drives the driver circuit 22 in order to vary the (average) duration of the interval TON1 with respect to the (average) duration of the interval TOFF1. In fact, the (average) voltage VOUT of an “ideal” boost converter (without losses) may be calculated based on (the average value of) the ratio D=TON1/(TON1+TOFF1), which essentially corresponds to the duty-cycle of a PWM signal:VOUT=VIN/(1−D)  (1)
FIG. 3 shows a second example of a boost converter. Specifically, in the example considered, the diode D of FIG. 1 is replaced with a high-side (power) transistor Q2, which is selectively opened or closed as a function of a drive signal DRV2. For example, in the example considered, the transistor Q2 is a field-effect transistor FET, such as a metal-oxide-semiconductor field-effect transistor (MOSFET). Due to the voltage levels at the transistor, often a p-channel FET (e.g. a PMOS) is used for the transistor Q2.
Specifically, in the example considered, the drain terminal of the transistor Q2 is connected (e.g. directly) to the node Lx and the source terminal of the transistor Q2 is connected (e.g. directly) to the terminal 104a. FIG. 3 shows also the direction of the body diode DQ2 which permits a current flow from the drain terminal to the source terminal of the transistor Q2.
The control circuit 20, in particular the driver circuit 24, is thus configured to generate also the drive signal DRV2. Specifically, the control circuit 20/driver circuit 24 is configured to open the transistor Q2 when the transistor Q1 is closed. Conversely, when the transistor Q1 is opened, the transistor Q2 should remain closed (similar to a diode) at least as long as the voltage at the intermediate point between the inductor and the transistor Q1 is greater than the output voltage VOUT.
For example, when using the Continuous Conduction Mode (CCM) (as shown in FIG. 2b) or Transition Mode (TM), the driving of the transistor Q2 may be simplified and the control circuit 20/driver circuit 24 may close the transistor Q2 when the transistor Q1 is opened. Accordingly, the switch-off duration TOFF2 of the transistor Q2 may correspond to the switch-on duration TON1 of the transistor Q1, and the switch-on duration TON2 of the transistor Q2 may correspond to the switch-off duration TOFF1 of the transistor Q1.
The above operation assumes the traditional operation of a boost converter as step-up converter as shown with respect to equation (1), i.e. for VIN<=VOUT. However, the converter shown in FIG. 3 may also be used when the input voltage VIN is greater than the output voltage VOUT, i.e. VIN>VOUT. Specifically, in this case, the converter may be operated in the so-called down-mode or down conversion mode operation.
For example, as shown in FIG. 3, the body diode DQ2 bypasses the transistor Q2. By a suitable connection of the transistor Q2 (e.g. by connecting the gate and the bulk terminals of the transistor Q2 to VOUT), during the switch off duration TOFF1 of the switch Q1, the voltage VLx at the node Lx will correspond substantially to VOUT+0.7 corresponding also to VOUT+VTQ2 (threshold voltage of Q2). Thus, the diode DQ2 is closed and the current provided by the inductor L will flow both through the diode DQ2 and the transistor Q2 and charge the capacitor COUT increasing the output voltage VOUT. Accordingly, when connecting the gate and the bulk terminals of the transistor Q2 to VOUT, the electronic converter may operate withVIN<VOUT+0.7 V. 
Such an operation and also other schemes of operation (e.g. using a different connection of the gate and bulk terminals of the transistor Q2) of the down-mode are known in the art, e.g. from documents U.S. Pat. No. 5,751,139, US 2004/0135556 A, EP 0 933 865 A1 or Christian V. Schimpfle, et al. “A Step-Down Conversion Concept for a PWM-mode Boost Converter”, Texas Instruments Deutschland GmbH. http://www.ti.com/lit/wp/slva144/slva144.pdf, which are incorporated herein by reference.
Generally, in order to operate a boost-converter in step-up mode and possibly also in down-mode, it may be required to monitor (as alternative or in addition to the voltage VOUT) the output current IOUT provided to a load connected to the terminals 104a and 104. For example, as mentioned before, the output current IOUT may be monitored instead of the voltage VOUT in order to generate the feedback signal FB for an output current regulation loop 22/24. Conversely, the output current IOUT may be monitored in addition to the voltage VOUT used by an output voltage regulation loop 22/24 in order to determine the load status of the converter, e.g. in order detect an open load condition (no load is connected to the terminals 104a and 104b) or a short-circuit condition (terminals 104a and 104b are short-circuited), in which the converter may be switched off at least temporarily.
Moreover, the load status may be used to adapt one or more operating parameters of the converter in order to improve the efficiency of the converter. For example, as mentioned before, the load status may be used to switch the operation of the converter from PWM mode to burst mode. Similarly, depending on the current level provided to the load, only certain portions of Q1 and Q2 may be used (e.g. when using plural switches connected in parallel in order to implement the switches Q1 and Q2). Thus, in light load conditions, only a little portion of the power is used in order to reduce switching power losses and increase the overall efficiency. Moreover, the current level may also be used to decide whether a further converter inside the same chip should be activated.
For example, as mentioned before, the output current IOUT may be monitored via a shunt resistor connected in series with the terminals 104a and 104b. However, this has the disadvantage that also such a shunt resistor generates electrical losses.
Thus, it would be advantageously to monitor the current flowing through an already existing component of the converter. For example, the average output current <IOUT> corresponds also to the average current <IM> flowing through the p-channel FET Q2. Thus, the current IOUT may be monitored by measuring indeed the current IM flowing (in average) through the p-channel FET Q2.
However, the transistor Q2 usually has a low switch-on resistance. Accordingly, when the transistor Q2 is closed, only a small voltage drop is developed at the terminals of the transistor Q2 due to the current IM flowing through the transistor Q2. Conversely, when the transistor Q2 is opened and the transistor Q1 is closed, the (significantly greater) output voltage VOUT is applied at the terminals of the transistor Q2.
Accordingly, a current sensing circuit is required, which is able to monitor the current IM flowing through the p-channel FET Q2 for all operating conditions of the converter. For example, for this reason, a simple differential amplifier connected to the terminals of the transistor Q2 may not be sufficient.
Similarly, it may also be required to measure the current flowing through a n-channel FET, such as the transistor Q1.